Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is________.

Correct Answer:

2.15 to 2.18

Solution:

Given:
Non-pipelined processor operating at 2.5 GHz
i.e. frequency = 2.5 GHz so, T = 1frequency=12.5 x 109 where T = Time

Similarly, pipelined processor operating at 2 GHz
i.e. frequency = 2GHz so, T = 12 x 109 where T = Time

Let total instructions = 100

In a non-pipelined processor, all 100 instructions will take 5 clock cycles each to complete.
So, Number of cycles = (100 × 5) cycles.

Total time taken by the non-pipelined process to finish executing 100 instructions
= 100×5×12.5 ×109
= 2 × 10-7

In a pipelined processor, the number of cycles

= 30×5100×51+95100×1+60×1+10×50100×3+50100×1  
= 105 + 60 + 20
= 185 cycles

Total time taken by the pipelined process to finish executing 100 instructions
=185×12×109
=0.925 × 10-7

speedup = Time taken by non-pipelinedTime taken by pipelined
=2×10-70.925×10-7=2.16